Non-Volatile Storage Systems with Go To Sleep Adaption

ABSTRACT

A non-volatile memory system goes into a low-power standby sleep mode to reduce power consumption if a host command is not received within delay period. The duration of this delay period is adjustable. In one set of embodiments, host commands can specify the delay value, the operation types to which it applies, and whether the value is power the current power session or to be used to reset a default value as well. In other aspects, the parameters related to the delay value are kept in a host resettable parameter file. In other embodiments, the memory system monitors the time between host commands and adjusts this delay automatically.

BACKGROUND OF THE INVENTION

This invention relates, generally, to non-volatile memory devices and,more specifically, to such device which optimize their behaviors basedupon host behavior.

Various commercially available non-volatile memory cards that arebecoming popular are extremely small and have different mechanicaland/or electrical interfaces. Examples include the relatedMultiMediaCard (“MMC”) and Secure Digital (“SD”) memory cards that areavailable from SanDisk Corporation of Sunnyvale, Calif., assignee of thepresent application. There are other cards that conform to standards ofthe International Organization for Standardization (“ISO”) and theInternational Electrotechnical Commission (“IEC”), an example that iswidely implemented being known as the ISO/IEC 7816 standard.

The physical and electrical specifications for the MMC are given in “TheMultiMediaCard System Specification” that is updated and published fromtime-to-time by the MultiMediaCard Association (“MMCA”) of Cupertino,Calif. Versions 2.11 and 2.2 of that Specification, dated June 1999 andJanuary 2000, respectively, are expressly incorporated herein by thisreference. MMC products having varying storage capacity up to 64megabytes in a single card are currently available from SanDiskCorporation, and capacities of 128 megabytes are expected to beavailable in the near future. These products are described in a“MultiMediaCard Product Manual,” Revision 2, dated April 2000, publishedby SanDisk Corporation, which Manual is expressly incorporated herein bythis reference. Certain aspects of the electrical operation of the MMCproducts are also described in co-pending patent applications of ThomasN. Toombs and Micky Holtzman, Ser. Nos. 09/185,649 and 09/186,064, bothfiled Nov. 4, 1998, and assigned to SanDisk Corporation. The physicalcard structure and a method of manufacturing it are described in U.S.Pat. No. 6,040,622, assigned to SanDisk Corporation. Both of theseapplications and patent are also expressly incorporated herein by thisreference.

The newer SD Card is similar to the MMC card, having the same sizeexcept for an increased thickness that accommodates an additional memorychip. A primary difference between them is that the SD Card includesadditional data contacts in order to enable faster data transfer betweenthe card and a host. The other contacts of the SD Card are the same asthose of the MMC card in order that sockets designed to accept the SDCard will also accept the MMC card. The electrical interface with the SDcard is further made to be, for the most part, backward compatible withthe MMC product described in version 2.11 of its specificationreferenced above, in order that few changes to the operation of the hostneed be made in order to accommodate both types of card. Certain aspectsof the SD card are described in U.S. patent application Ser. No.09/641,023, filed Aug. 17, 2000, which application is incorporatedherein by this reference.

Cards made according to the ISO/IEC 7816 standard are of a differentshape, have surface contacts in different positions, and a differentelectrical interface than the MMC and SD Cards. The ISO/IEC 7816standard has the general title of “Identification cards-IntegratedCircuit(s) Cards with Contacts,” and consists of parts 1-10 that carryindividual dates from 1994 through 2000. This standard, copies of whichare available from the ISO/IEC in Geneva, Switzerland, is expresslyincorporated herein by this reference. ISO/IEC 7.816 cards areparticularly useful in applications where data must be stored in asecure manner that makes it extremely difficult or impossible for thedata to be read in an unauthorized manner. The small ISO/IEC 7816 cardsare commonly used in cellular telephones, among other applications.

Current storage systems are designed to work with a number of differentapplications, such as audio storage, still image storage and videostorage, but are generally not optimized for a particular application.The different hosts use memory cards in different applications. Theseapplications have different needs in terms of read and writeperformance, level of data integrity, and so on. Such systems mayoperate well in one application, but fail to provide acceptableperformance in another application. The differentiation in theapplications needs is not taken into account in the card controller.

These removable non-volatile memory cards include a memory array and acontroller that performs as the memory control and the host interfacefunction. These removable cards are plugged into different a variety ofdevices, such as personal data assistants (PDAs), digital camera, cellphone, etc., which access the card in different patterns. Thisdifferentiation causes the card to have less than optimal performanceand capability to optimize the memory management algorithms according tothe host access pattern for the various applications. Although generalperformance enhancements, such as caching, may help in manyapplications, there will still be trade offs in a general-purpose card.Alternately, there may be specific optimizations for certainapplications, but these need to be engineered into the card ahead oftime.

SUMMARY OF THE INVENTION

According to a first set of aspects, a method is presented of operatinga non-volatile memory system, where the memory system includes anon-volatile memory circuit and a controller circuit for managing datastored in the non-volatile memory circuit and the interactions betweenthe memory system and a host to which the memory system is connected.The method includes, while connected to the host, operating of thememory system by the controller circuit in one of either a standard modeor a low-power standby mode. The memory system operates in the standardmode when executing host commands and, after executing a host command,lapsing from the standard mode into the low-power standby mode after adelay unless receiving a further command from the host prior to lapsinginto the standby mode. In response to receiving a host command while inthe standby mode, the memory system reverts to the standard mode. Themethod further includes, while connected to the host, operating thememory system according to a set of host commands, wherein the set ofhost commands includes one or more commands that specify a value for thedelay subsequent to the execution of them.

According to other aspects, a non-volatile memory system comprises anon-volatile memory circuit and a controller circuit connected tonon-volatile memory circuit. The controller circuit manages the transferof data between the memory circuit and a host to which the memory systemis connected and the storage of the data on the memory system. Thecontroller circuit includes logic circuitry and a volatile random accessmemory. In response to the memory system not receiving a host commandwithin in a period of time specified by a delay parameter, thecontroller places the memory system into a low-power standby mode. Thecontroller maintains a first value for the delay parameter in thenon-volatile memory circuit, and the controller resets the value of thedelay parameter in response to a command that specifies a value for thedelay parameter different than the first value.

Further aspects include a method of operating a non-volatile memorysystem, the memory system including a non-volatile memory circuit and acontroller circuit for managing data stored in the non-volatile memorycircuit and the interactions between the memory system and a host towhich the memory system is connected. The controller circuit operatesthe memory system in one of either a standard mode or a low-powerstandby mode, and the memory system executes commands from the host inthe standard mode and lapses from the standard mode into the low-powerstandby mode after a delay value unless receiving a further command fromthe host prior to lapsing into the standby mode. The method includesmonitoring by the controller of a plurality of commands from the host tothe memory system; based on said monitoring, determining the timebetween the commands; and optimizing by the controller of the delayvalue based on the time between the commands.

Various aspects, advantages, features and embodiments of the presentinvention are included in the following description of exemplaryexamples thereof, which description should be taken in conjunction withthe accompanying drawings. All patents, patent applications, articles,other publications, documents and things referenced herein are herebyincorporated herein by this reference in their entirety for allpurposes. To the extent of any inconsistency or conflict in thedefinition or use of terms between any of the incorporated publications,documents or things and the present application, those of the presentapplication shall prevail.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a system in which a non-volatile memory card isutilized.

FIG. 2 shows the pin assignments of an example card and system socket inwhich the card is inserted.

FIG. 3 is a block diagram showing more detail of an exemplary host-cardsystem.

FIG. 4 illustrates an exemplary host access pattern.

FIG. 5 describes an exemplary quality of service negotiation.

FIG. 6 is a flow chart of an exemplary embodiment.

FIG. 7 illustrates an exemplary host access pattern and how access timecan be reduced.

FIG. 8 is a flowchart of an exemplary embodiment where the memory devicemonitors the host delay time and adjusts go-to-sleep delay valuesaccordingly.

DESCRIPTION OF SPECIFIC EMBODIMENTS

With reference to FIG. 1, a host electronic system 31 is illustrated toinclude a socket 33 into which one or more types of commerciallyavailable removable electronic circuit card 35, such as the memory cardssummarized in the Background above, may be inserted and removed by theuser. The socket 33 may be built into the host 31 or physically separateand connected by a cable or cableless means. The host 31 may be apersonal computer, in desktop or notebook form, which includes thesocket 33 that receives such a card. Other examples of host systemscontaining such a card socket include various portable electronicdevices, such as hand held computers, personal organizers, otherpersonal digital assistants (“PDAs”), cellular telephones, musicplayers, and the like. Additionally, auto radios and global positionsystem (“GPS”) receivers also can have such a memory card socket. Theimprovements of the present invention have application to a wide varietyof host systems that include a memory card socket or to which anappropriate adaptor or connector may attach a memory card.

In most of the examples described herein, the SD card is described butit will be understood that the invention is not limited toimplementation with any specific type of removable electronic circuitcard. In FIG. 2, the physical configuration of a SD card 35 and a matingsocket 33 are shown. The SD card is rectangular in shape, havingdimensions of 24 millimeters by 32 millimeters, with a thickness of 2.1millimeters and narrow rails (not shown in FIG. 2) along the longersides of the card that are 1.4 millimeters thick. The present inventionmay be implemented with a card having one of a wide variety of sizes buthas a high degree of usefulness with cards that are 51 millimeters orless in length, 40 millimeters in width and 3 millimeters in thickness.

The SD card 35 contains nine surface electrical contacts 10-18. Contacts13, 14 and 16 are connected to power (V_(SS), V_(DD) and V_(SS2)) wheninserted into the host system socket 33. Card contact 15 receives aclock signal (CLK) from the host. Contact 12 receives commands (CMD)from the host and sends responses and status signals back to the host.The remaining contacts 10, 11, 17 and 18 (DAT 2, DAT 3, DAT 0 and DAT 1,respectively) receive data in parallel for storage in its non-volatilememory and send data to the host in parallel from the memory. A fewernumber of data contacts are selectable for use, such as a single datacontact 17. The maximum rate of data transfer between the host and thecard is limited by the number of parallel data paths that are used. TheMMC card described in the Background above has a similar contact layoutand interface, but omits the data pins 10 and 18 and does not use thecontact 11, which is provided as a spare. The MMC card has the samedimensions and operates similarly to the SD card except that the card isonly 1.4 millimeters thick and has a single data contact 17. Thecontacts of the card 35 are connected through respective pins 20-28 ofthe socket 33 to its host system. Other extensions of memory cards thatare compatible with the present invention are described in U.S. patentapplication Ser. No. 09/924,185 filed Aug. 2, 2001, which is herebyincorporated by reference.

The exemplary embodiment of the present invention is based on removableelectronic circuit card, structured such as that shown in FIG. 3. FIG. 3shows a conventional system having data processed by the host unit andthen transmitted to the PC card for storage. As shown in the figure, thesystem comprises two units: a host unit 160 and a card unit 100, forexample a standard MultiMediaCard or SD card. Generally, the host unitcan be a consumer apparatus such as a cellular phone, a PDA, a PalmPilot, or a personal computer. The host unit 160 comprises a processor162 and other supporting components, such as a host memory 163, a timer164, and a number of other standard elements not shown here.Furthermore, the host unit further comprises a card interface 161 forcommunicating with the card unit 100. The host interface 161 can beimplemented using any of the above-mentioned protocols defined by thevarious manufacturers or associations.

As shown in more detail in FIG. 3, the card unit 100 generally comprisesa host interface 141, memory storage and, in some cases, an on-cardmicro-controller. For the example shown, the host interface 141 of thecard unit is used for communicating with the host unit 160. The on-cardmicro-controller 131 is used to control the loading of data from thehost unit to the memory storage. In addition, the controller is designedfor handling memory functions such as addressing and buffering. Thecontroller 131 and host interface 141 are connected to the card bus 153,to which may also be connected some non-programmable ROM memory 123 forprogram storage and a RAM memory 121, usually volatile, that can act asa cache, as described for example in U.S. Pat. No. 5,418,752 and U.S.Pat. No. 5,172,338, which are both hereby incorporated by thisreference. The mass storage memory 111, that will be FLASH memory on aMultiMediaCard or SD card, is not connected directly to the bus 153, butis instead connected through 155 to mass storage interface 115, which isin turn connected to bus 153. The mass storage interface 115 serves as a“non-linear” or “non-random” access interface for controlling the FLASHmemory where data is stored in a non-linear fashion.

Memory cards are used in a wide variety of applications storingdifferent types of data that have different requirements. These includeaudio, video, digital camera, data capture, error free applications(e.g., medical data) and so on. Although current storage systems aredesigned in a general manner to work in a number of differentapplications, such as audio storage, still image storage and videostorage, they may operate well in one application but fail to providefully acceptable performance in another application.

The present invention provides for a variety of cards that may beoptimized for a single application or several different applications.For example, an audio-optimized card would “sense” when it is used in anaudio device, such as an MP3 player, and know that it will need tomaintain a certain data rate output, but may not be required to writedata often. Given such information, the controller of the card canperiodically output data, and during the dead times performshousekeeping functions and/or go into low power mode. Similarly, avideo-optimized card can be developed that could either “sense” it isbeing used in a video application or, alternatively, the host can informthe card of the fact. A video-optimized card will take other informationpassed from the host into account, such as: record data rate(s), playback data rate(s), format, compression, quality criteria, sound criteriaand other information related to video-applications. Knowing thesefactors will allow the card to perform optimally for thevideo-application.

For example, some applications can tolerate more error than others. Suchapplications, such as a fax or some video applications where singlepixel errors are not that noticeable, would not require completelylossless ECC. The memory device can poll the host system to determinewhether such a lossy scheme is acceptable. Another example where theloss of a few bits in a sector is not critical is the playing of a codedvoice that is saved on a memory card because the decoding can becompensated by the interpolation that is done on data, with eachcoder/decoder can define its threshold number. On the other hand, moreintensive ECC can be performed in applications where data integrity isessential (e.g. medical applications). In this case, the memory deviceemploys more complicated ECC at the cost of performance. Such variableECC or quality of service ECC is one example of card adapting to thehost. Although this may be determined based upon polling the host, thecard may also adapt to the host based on the card profiling the host.

In a host profiling arrangement, the non-volatile memory system profilesthe host system with which it is used in order to determine the mostefficient method of communicating with the host system. The host systemof the non-volatile memory system provides feedback to the card toexchange information about a number of criteria. This information couldinclude the type of drivers installed on the host and statistics relatedto those types of drivers, such as whether they are for video, audio,still images, and so on. It could also include the maximum and minimumclock rates or information about the buffer in the host device (whetherthe host wants to use the buffer or not) or the buffer in non-volatilesystem (whether the host wants to use the buffer on the non-volatilesystem). Based upon the profile of the host established by the card, thecard can optimize itself accordingly.

As an example, consider the case where the card would optimize itselfbased on the frequency of host reads and writes for a card used in anMP3 player. MP3 players do not write often, but they do read a lot, asopposed to cameras that write often and frequently down load to a PC orPDAs that both read and write frequently. Additionally, MP3 players readfairly regularly and not at great speed. Consequently, there is a lot ofnon-busy time during reads, as shown in FIG. 4.

FIG. 4 is a schematic representation of the access pattern of an MP3player as a function of time, where data is read at 401, 403, 405, andso on, with the dead time between a pair of reads indicated at 411.During these dead times, the controller can go into a power saving mode,engage in defect management or various heroics to save marginal data, orfix bad bits or sectors as these non-busy times have a fairly regularoccurrence and duration. Similarly, the profiling information of thehost can give the card the ability to decide what are the bestoperations to do for the best performance of timings, quality, powerconsumption, and so on.

In any of these host-profiling methods, the card controller willidentify the host access profile to optimize its algorithms. In additionto a memory array 111 (FIG. 3), the card will include a processor-basedcontroller 131 that performs as the memory control. Although the memorycan be based on other technologies, the exemplary embodiment will againbe based on a flash memory.

As noted, these cards are designed to be plugged into different devices,such as PDAs, digital cameras, cell phones, and so on, which access thecard in different patterns. In the prior art, this differentiation infunction causes the card a hit in performance and in the capability tooptimize the memory management algorithms according to the host accesspattern as the prior art lacks the algorithm optimization aspect of thepresent invention. The different hosts use different applications withthe memory cards. These applications have different needs in terms ofread/write performance, level of data integrity, etc. that is not takeninto account in the prior art card controllers. The host profilingaspect of the present invention improves upon the prior art by havingtwo modes of operation. In the first of these, the host profiling is bythe card controller. The second is based on a quality of servicenegotiation between the card and the host. These operations will allowthe card controller to tune its algorithms according to the datacollected on the host. The various embodiments can be implemented inhardware or firmware.

In the mode where the host profiling is performed by the cardcontroller, the card will learn about the host during its transactionsand will collect information, such as write/read buffer transfer speed,the idle time between data buffers, block count in read/write, LBArewrites, file access table (FAT) updates, idle time between sequentialcommands, and so on. The card will then use this information to optimizethe memory control algorithms to the host. For example, on a host thatreads slowly, such as an MP3 player, the card can handle correctable ECCerrors by having the card controller read ahead enough sectors that willallow a safe correction in the flash memory without a degradation inperformance. In another example, if the card recognizes rewrites to thefile access table, it can have FAT data caching in the card and updatethese sectors less frequently.

A first example of host profiling by the card's controller is theprofiling of the clock rate used on the card's system bus, for examplethe SD or MMC bus as described in the references incorporated above forthese cards. In this example, the card's hardware can include a counterthat will be incremented on every system bus clock. Such a counter 133is shown in FIG. 3 as part of the controller. As the system's firmwareknows the system's clock rate that the controller is running, a simplecalculation allows the controller to determine the bus clock. In anotherexample, the card's firmware can activate a timer to measure how long ittakes the card to receive from or send to the host a specified number ofsectors. This number could be any number (2, 4, 8, 16, and so on) andcan be a settable parameter in firmware.

In a further example, the card can set its system clock (or clocks) tomeet the host's transfer rate and minimize power consumption. As thehigher the clock rate, the greater the power consumption of the card'scontroller, the controller's system clock(s) have a major impact overthe card's power consumption. If the card system maintains a clock ratefaster than needed to conform with the host's transfer rate, unnecessarypower will be consumed, so by setting the system clock settings to meetthe host transfer rate, the card optimizes its power consumption whilemaintaining performance. The card's firmware can hold a table toindicate the card's data transfer rate for a given clock setting. Oncethe card's profiling has determined the host's transfer rate, it canthen use the minimum clock rates that allow the card to successfullysupply the host's data transfer rate. This will allow the card's powerconsumption to be optimized. The firmware can continue to monitor thehost's data transfer rate and update the controller's clock(s)setting(s) accordingly.

In another set of examples, the card can profile a host's block countfor both read and write. Again referring to the SD and MMC cards as theexemplary embodiment, the write and read commands do not have a definedblock count and the termination of an operation is based on a stoptransmission command. In a first instance, during a reset process, suchas power on, the card's firmware can determine whether an access by thehost is to the file system area instead of the user data area. At reset,the firmware can read assigned area where the Master Boot Record (MBR)is stored, such as Logical Block Address (LBA) 0. If the master bootrecord is a file system sector, the firmware can find the LBA range ofthe file system, such as (MBR+Partition Table+FAT1+FAT2) in the MMC/SDcard example, where FAT1 and FAT2 are the two copies of the file accesstable. Once the LBA range of the file system determined, any access tothis address space by the host can be considered as access to filesystem area and not to user area.

In a second instance, the firmware can find the block count used by thehost to write data to the user space during write or read operations andthe sequence of starting LBAs. Once the card's firmware has determinedthe block count that the host uses and the sequence of starting LBAs, itcan tune its algorithms and hardware to maximize performance andminimize power consumption. Examples of such tuning can include datacaching, prioritizing tasks/interrupt service routines/direct memoryaccesses, determine garbage collection (data relocation) preferences(such as least recently used or most recently used blocks), and so on.In systems having multiple Direct Memory Access (DMA) and InterruptService Routine (ISR) operations, the priority order chosen can have amajor impact on performance.

In the quality of service mode, the host requests the card report itscapabilities and recommendation. The host will report to the card theconfiguration it prefers to work with and its profile for accessing thecard. The card capabilities reported to the host can include: read/writespeed, best write block count, best start logical block address (LBA)alignment, ECC capabilities correct/ignore/abort, performance versuscurrent consumption, performance versus data retention, and otheroperating parameters. There are usually a number of trade offs betweenthese in card design, and this process allows these parameters to beadapted to the particular application. The host profile reported to thecard can include: write/read maximum speed; logical address offsets fordata types (for example, the offset in number of blocks for user datawith a start LBA and block count due to overhead, such as (blocksdevoted to list of transactions+start LBA+block count) or (blocksdevoted to FAT area−start LBA+block count); the level of data integrityin acceptable in a read (for example, ECC errors can be corrected or canbe ignored and the read continued; alternately, a bad block can be setto some pattern or the read can be aborted); and so on. All of thefeatures described above for the host-profiling mode can also beimplemented in the quality of service mode and vice versa. Additionally,it should be noted that these two modes are not exclusive of each otherand be used in a complimentary manner.

As an example of the quality of service mode, if the card knows thememory area storing FATs, it can use a different algorithm to write tothese FAT blocks to minimize garbage collections. In another example, ifa host, such as a PC, requires high performance and has a high powersupply, the card can choose a high performance/high power consumptionmode, such as using multiple plane or multi-chip programming (describedin U.S. patent application Ser. No. 10/315,451, filed Dec. 9, 2002,which is hereby incorporated by reference); on the other hand, in a lowpower host, such as an MP3 player, the card can choose low performanceand low power operation.

If the controller has the ability to adjust its own internal clockfrequency such as by writing a value to a defined hardware register, thecontroller performance can be adjusted to meet that required by theapplication and can even be varied depending on external conditions. Forexample, in a high performance application, a maximum frequency may bedesirable at the expense of increased power consumption, and anintelligent controller can measure suitable external variables such astemperature or power supply voltage and adjust the clock frequencyaccordingly. It is common to design an internal oscillator to berelatively constant with respect to temperature and voltage. However,CMOS circuits are normally capable of higher speed operation at lowertemperatures and at higher voltages. The chip temperature can bemeasured, such as through the use of a temperature sensitive resistor orp-n junction, and the frequency set accordingly. Similarly the externalvoltage is easily measured using well know analog to digital convertercircuitry and the internal oscillator frequency adjusted in response tothis measurement. In this manner the application can override thenormally pre-set clock frequency and obtain maximum performance under avariety of application and environmental condition.

FIG. 5 is a diagrammatic illustration of an exemplary host-card qualityof service negotiation process showing the exchanges that allow the cardto choose the quality of service optimized for a given application.After the card is connected to a host, the host sends the card a resetsignal 601. The reset signal in an MMC card embodiment is describedfurther in U.S. patent application Ser. No. 09/186,064 incorporatedabove, where the ability of the card to select the host's protocol basedupon the reset signal is described. The card responds with a readysignal 603. At this point the actually quality of service (QOS)negotiation begins, with the host sending its QOS capability data to thecard 605 and requesting the cards QOS capabilities 607, where the orderof these steps can be switched depending on the implementation. The cardresponds to the host with the card's QOS data 609. At this point, thehost can put the card use in an application.

After the QOS negotiation between the host and the card, the host canset the card's configuration according to the host applications' needs.For instance, an MP3 application may require only require a low bit rateand low power, while an image-capture application may require themaintaining high bit rate, and so on. For example, to use the card in afirst application APP 1 610, the host sets the card's QOS 611 optimizedfor the application: for example, it could be an application were therate and consistency of data transfer is more important that minoramounts of error. In this case, the use of ECC could be used only in asmuch as it does not affect the transfer rate. At a subsequent time, thehost can use the card in another application APP N 620 and resets thecard's QOS 621 accordingly: For example, application APP N could requiredata, such as in medical imaging, to be stored at with highest integritywith speed of far less importance.

All of these embodiments have the card learning host profile in realtime and tuning the memory management algorithms according the collectedinformation for achieving the best performance. They also differ fromthe prior art in that the host and card negotiate over capabilities andthe card sets the card operating algorithms according to the bestconfiguration.

A particular implementation of the invention based on dynamicoptimization through pattern recognition is described with respect toFIG. 6. The exemplary embodiment of FIG. 6 allows the performance ofstorage devices to be optimized without having to analyze an overlylarge number of applications by allowing the storage device todynamically self-optimize by monitoring for specific and typicalpatterns of host behavior. This improves upon prior art techniques, suchas caching and other general performance enhancements. Although thisimplementation is again discussed in the context of a flash basednon-volatile memory card, as are the various aspects and implementationsdiscussed above, these concepts may be applied to other storage devices,such as in the optimization of dual storage devices such as a disk drivewith flash memory device.

The techniques of the embodiment of FIG. 6 allow a storage device tomemorize access sequences issued by the host under certain predefinedconditions, such as host reset, power on boot sequence, variousbenchmarks and so on. The underlying concept is that when thesepredefined condition or “trigger patterns” occur, the sequence of hostcommands that follow them is usually identical. It should be noted thatthis matching is based on pattern matching, rather some sort of codematching mechanism. The storage device can use this information tooptimize operation for those expected commands. Optimization could be byperforming look ahead read caching to pre-fetch data, or other systemtype preparation that would speed up command execution. For example,when a host issues a reset, the portion of the memory storing the fileaccess tables are most likely read first, so the card could use this asa trigger. On deviation from expected command or control sequence, thedevice would memorize the new command sequence and save to permanentstorage thus becoming self-adaptive. Similarly, if an already storedpattern is changed, the stored pattern is updated to reflect thevariation or extension of the pattern. Several different patterns andcommand sequences may be stored.

Referring to FIG. 6, the process starts at 501 with the card connectedto the host and at step 503 any initial or additional set of patternsand command sequences are loaded onto the card. When used with a blankcard, a number of such patterns may be predefined in firmware, althoughthese need not be complete patterns. As the implementation isdynamically self-optimizing, the card itself can complete the process,thereby saving on initial engineering time. Typical patterns couldinclude command sequences and single commands, reset, power cycle, andso on. During operation, the card will monitor the host-cardinteractions at step 505, seeing whether a match occurs with any of thestored patterns. This continues (the “No” loop from 507) until a matchis detected at step 507, when it moves to step 509.

When a pattern matches the initial portion of a stored command sequence,the card can pre-execute the command sequence corresponding to pattern,as shown at step 509. The actual action taken may depend uponimplementation and may be actions in preparation for the command or theactual execution of the command, such as a read operation to fill acache or doing a seek to an expected location in the memory, preloadingcontrol information or tables, or performing logical to physical addresstranslations. Controller 131 (FIG. 3) would handle the processinginvolved in these processes. As the host commands continue to come in,the card will check the command against the stored command sequence list(step 511) and determine (step 513) if the command previously selectedas matching in step 507 based upon its initial portion continues tocorrespond. If so, the command will be executed in step 517 using theprevious optimization. If not, nothing is lost and the process goes tostep 515 where the card determines if the end of the list has beenreached and, if so, to return to monitoring the host at step 505. Notethat for the case where the entries of the list have an order, such aseries of logical block addresses to read, it can be determined that thecommand does not match a list entry without having to exhaust the list.

If step 515 finds that it is not the end of the list, the flow continuesto step 519 for the dynamic updating portion of the process. In step519, the command is executed and the new sequence is stored in thememory, such as RAM 121 of FIG. 3, so that it can be saved to thecommand list when it is updated. It the list has not been previouslyexhausted, this process continues (the “No” loop from 521) until the endof the list is reached, as determined in step 521, at which point thelist of saved commands is updated (step 523). For example, if thesignature access of a benchmark changes so that its later portion isdifferent than the previous value (say, switching a logical address tobe read), this would be covered in the updating by revising this portionof the benchmark sequence. Once the updating is complete, the processreturns to step 505 and monitors the host.

For example, consider the case where a non-volatile memory is organizedinto a series of “zones”, such as is described in U.S. patentapplication Ser. No. 10/315,451 filed Dec. 9, 2002, which is herebyincorporated by reference. In this arrangement, various data used aspart of the boot process, such as the file access table (FAT), is storedin a specific area, which can be taken as part of zone 0. When initiallyaccessing a given zone, there is an initial process of logging in tothat zone. For example, there may be initial header data associated witheach zone that needs to be read (logical to physical conversions,remapping, etc.) and processed before the actual data content isretrieved. By performing this login ahead of time and pre-fetching anylikely data, this time is saved if the sequence is as expected, andnothing is lost if it turns out to be different.

FIG. 7 can used be to illustrate this situation, where the top rowillustrates the prior art process and the bottom row shows how thiswould be changed from the prior art. The top row of FIG. 7 is similar toFIG. 4, but with additional detail. The controller receives a command orcontrol sequence (451 a, 453 a, 455 a, . . . ) and responds. Eachresponse consists of a corresponding preparation portion (451 b, 453 b,455 b, . . . ) and operation portion (451 c, 453 c, 455 c, . . . ). Inthe prior art, the controller will wait for the command, such as 453 a,before executing the corresponding preparation and operation, 453 b and453 c. In the present invention, once the initial portion of the commandor control sequence matches one of the trigger patterns, the subsequentpreparation portions can be moved into the dead time ahead of the nextcommand, as is shown in the bottom row of FIG. 7.

In the bottom row of FIG. 7, the controller finds a match in the controlsignal 451 a. As it had not previously established this as matching astored pattern, the corresponding preparation and operation phases (451b, 451 c) are executed afterwards; however, the preparation for theexpected next command (453 b), such as caching data or a seek, is alsoexecuted prior to the arrival of the corresponding signal 453 a at thecontroller. If the signal 453 a continues to match the pattern, thepreparation phase is already completed and the controller proceedsdirectly to the operation 453 c. (If 453 a is not a match, thecorrection preparation phase would be performed as in the top row andnothing is lost and the stored sequence can be subsequently updated) Theprocess continues similarly for the set 455 a-c and so on for the restof the control sequence. This results in the hiding the preparation timefor each part of the sequence after the first where the pattern ismatched. For example, through 455 c in FIG. 7, the process has theresultant time saving of δt due to pre-executing the “b” portions of thecommands.

For example, consider a boot process, where zone 0 is most likely to beaccessed (to retrieve the FAT), followed by, say, zone 5 and then zone1. Based on the initial portion of the sequence, during the dead timeafter accessing zone 0, the controller may as well login to zone 5 andbe ready. If 451, 453, and 455 respectively correspond to the respectivecombined access times for zones 0, 5, and 1 in the exemplary process, bymoving the login and pre-fetch time (453 b in FIG. 7) into the precedingdead time, the access time needed for zone 5 is correspondingly reduced,with similar savings available in the other access times. If thesequence of commands does not go to the expected zone 5, as this loginwas performed during an idle time, nothing is lost. Additionally, if theboot process changes, from, say, the exemplary 0-5-1 to 0-5-3, or isextended, to, say, 0-5-1-4, this will be dynamically updated.

The dynamic optimization through pattern recognition described withrespect to FIG. 6 can either be left functioning once the memory systemis shipped and in the field, allowing for continued optimization duringuse by the consumer, or be used prior to shipping and then fixed. In theprior art, the standard method of optimizing a card at the factory for aspecific application or set of applications required a study of thehosts' access patterns. Once these had been analyzed, the cards'firmware was tuned accordingly. In contrast; the present inventionallows the storage device itself to learn. The storage device can startwith only a few partial patterns, or no patterns, stored on the device.The card can then be run through a number of applications, such asbenchmark utilities or boot sequences, and the corresponding patternslearned and stored. At this point, the learned processes could be fixedif desired and the product shipped.

Although the discussion so far has considered the adaptation of aremovable electronic circuit card to host behavior, more generally thecontroller can adapt to the card to other external conditions. Forexample, it is known that the performance of flash memories, such asthose found in the exemplary embodiments above, degrades when operatedat extreme temperatures. Further such examples of conditions external tothe memory card that may affect card operation are when the battery islow on host device. As noted above, chip temperature can be measured,such as through the use of a temperature sensitive resistor or p-njunction, and the frequency set accordingly. Similarly the externalvoltage is easily measured using well know analog to digital convertercircuitry and the internal oscillator frequency adjusted in response tothis measurement. In this manner the application can override thenormally pre-set clock frequency and obtain adjust performance to avariety of external conditions.

When the controller senses any of these additional conditions that mayadversely affect performance, the controller could operate the memory ina more reliable manner. This could be done in various ways similar tothose already described, such as lowering performance, increased use ofECC or margining, and so on. The sensing of such conditions can beaccomplished using reference cells in the memory or other techniques,such as described in U.S. Pat. No. 5,694,356, which is herebyincorporated by reference. The particular conditions to which thecontroller responds, and how it does so, would correspond to the memorytechnologies (e.g. thin film, MRAM, FRAM, NMOS, etc.) employed.

The forgoing examples memory systems have been based on flash EEPROMmemory cells have been described with respect to the type of cell thatutilizes conductive floating gates as charge storage elements. However,the various aspects of the present invention can be used in conjunctionwith the various alternate non-volatile memory technologies (such asthin film, MRAM, FRAM, NMOS, etc.) described in U.S. patent applicationSer. No. 10/841,379 filed May 7, 2004, which is hereby incorporated byreference. For example, the invention may also be implemented in asystem that uses a charge trapping dielectric as the storage elements inindividual memory cells in place of floating gates. Dielectric storageelements are also discussed further in the U.S. patent applicationserial number U.S. Ser. No. 10/280,352, filed Oct. 25, 2002, which ishereby incorporated by this reference.

The forgoing material is developed more thoroughly in U.S. Pat. No.7,427,027, U.S. Pat. No. 7,926,720, and US patent publication numberUS-2011-0167186-A1.

Go to Sleep Device Adaptation

This section considers embodiments related to when the non-volatilememory device goes into a low-power standby, or sleep, mode. Betweencommands, the device controller may go to sleep in order to save standbypower consumption. For example, the controller may same power by one ormore of turning off a clock or oscillator on the device, turning offpower to the memory section, turning off power to one or more areas ofthe controller (such as RAM blocks), and so on. Although the being inthe sleep mode saves power, returning the device to the normaloperational mode (“waking the device”) upon receiving a new command isboth time and power consuming. Although the specifics depend on thescope of the low-power standby mode, waking the device will negativelyaffect device performance, especially performance for more random hostaccesses of the device. Consequently, it would help to optimizeperformance if go to sleep behavior of the memory device better matchedthe access behavior the host. This section considers mechanisms thathelp minimize the occurrences of switching between modes and,consequently, minimize the performance impact and the currentconsumption by increasing the correlation of these mode changes to thehost's access timing.

In the typical prior art, if the memory device has a sleep mode, thedesign would use a fixed time delay (of some number of micro- ormilliseconds, for instance) before lapsing into a low power standbymode. This means that there will be no performance impact due toreturning to the regular operational mode if the host sends commandsmore frequently than the device delay. A disadvantage of thisarrangement is that it does not cover host command timings (from theprevious command termination) that are greater than the device delay,resulting in a too frequent lapsing into sleep mode; and, conversely,when the typical host command timing is less that the device delay, thememory system will tend to wait too long before lapsing into the sleepmode. This situation can be aggravated for the case running differentapplications that use different command timings.

A first set of embodiments uses a command between the host and thememory device to set the device's low-power standby mode switch delay(or go-to-sleep delay, STSD). The setting can be per operation or forany command. For instance, if the host is slower in accessing the deviceupon a set of write commands compared with a set of read commands, thehost can define different values for the sleep delays of writes andreads.

The command format can be:

Set Low_Power_Standby_Mode_Switch_Delay (Operation Type, Delay Time,Attribute) The Operation Type field specifies the types of commands towhich the delay applies, such read, write, erase, boot, and so on. TheDelay Time filed specifies the go-to-sleep delay number in, for example,microseconds. An Attribute field can be included to specify that delayis permanent or volatile:

Attribute—PERMANENT: This setting will be used as default after powercycle

-   -   VOLATILE: This setting is used for the current power session        The controller can keep the delay value or values in its RAM 121        (FIG. 3) or other volatile register memory. An initial or        default delay value (or values for differing operation types)        can be kept in non-volatile memory, such as in control data kept        in the non-volatile mass storage 111, where the PERMANENT        designation would cause the corresponding current default value        to be updated. While a VOLATILE designation would update the        value in RAM 121 only, the PERMANENT designation would update        both the value in RAM and that stored in non-volatile memory.

According to a second set of aspects, in some embodiments the low powerstandby mode switch delay (GTSD) is set in the memory system's parameterfile that holds various operational parameters used by the controllerduring the operation of the memory system. The values initially in theparameter file 171 (FIG. 3) will be the default values, residing in thenon-volatile memory 111, and copied into a portion 173 of the volatileRAM 121 at initialization rime. The host can then change these values atany time, as described above.

In a complementary set of embodiments, the device monitors the hostdelay time automatically, acting as a learning system. Based on thismonitoring, the controller can adjust the delay values to optimize thememory systems algorithms for going to sleep with respect to the host'sbehavior. In an exemplary embodiment, the input values are:

Default GTSD value—Initial GTSD value after power up from parameter fileor host

-   -   Maximum GTSD value—Maximum GTSD value from parameter file or        host        The variables used are:    -   Current GTSD (C-GTSD) value        After power up this variable equals the default GTSD value and        then the value changes after each command as described below        with respect to FIG. 8.

FIG. 8 is an exemplary flowchart for the process. Initially, the defaultdelay (GTSD value), as passed form the host or parameter file, is usedas the current GTSD (C-GTSD) value (801). When a command ends, thesystem is delayed by the time value in C-GTSD before it lapses into thelow-power standby mode. The next command can arrive before the system isswitched to low-power standby mode or when it is already in this mode.At 803 a command is received and the path taken is determined by whetheror not the command came during the delay period or after the device hasgone to sleep. This can be from 801 if just after initialization or onthe loop back from 809 or 817.

If the next command arrives before the system is switched to low-powerstandby mode (“YES” path out of 803), the new C-GTSD value is calculated(805) based on this fact. This can be done by an algorithm based on thecurrent C-GTSD value and the amount of time after the preceding commandwhen the next command arrived (TNC). (If this is the first command afterinitialization, the time since initialization can be used as the TNCvalue or this step can be skipped for this first command.) For example,one sample algorithm is:

C-GTSD=(C-GTSD+TNC)/2.

In this example, the average of the two values is used, but moregenerally other intermediate values can be used, and can be a settableparameter for the system or dynamically determined by the controller.Also, more complicated algorithms may be used that are based more thanone TNC value, although this will require more storing more data andmore involved computations.

This new value is then saved (807) as the current GTSD value andreceived command is processed (809). At 807, the current delay (C-GTSD)is stored in RAM and, depending on the embodiment, stored innon-volatile memory as the new default value, much as described abovefor the host command based embodiment. Although shown as occurringsequentially in the order 805-807-809, the order can be arranged,including having these steps overlap. After processing the command and809, the memory system then loops back to 803 and waits until the nextcommand comes in.

If the next command arrives when the system is already in low-powerstandby mode (“NO” path out of 803), the memory system will haveswitched to the low-power standby mode while waiting for the nextcommand, at which point it will revert to the full power, regular mode(811). The new C-GTSD value can be calculated (813) by an algorithmbased on the current C-GTSD and the maximum GTSD (M-GTSD) value,increasing it from the current values part way toward the maximum. Oneexample for an algorithm is:

C-GTSD=C-GTSD+(M-GTSD−C-GTSD)/10.

This adds some to the C GTSD value, without taking it beyond themaximum. Other shifts besides a tenth could similarly be used, as longas it does not reach the maximum, and this fraction can be a settableparameter for the system or dynamically determined by the controller. Aswith 805, more complicated algorithms could also be used based more thanone inter-command period. The process then proceeds on to 815 and 817,which are much as in 807 and 809 and for which similar comments apply.

The flow of FIG. 8 is similar to that for first embodiments discussed inthis section, where the delay is set based on a host command, exceptthat steps 805 and 813 reset the delay based upon the command, if thecommand specifies a delay as described above, and do nothing if thecommand does not specify a new delay value. As noted above, the commandbased embodiments are complimentary to the controller determined delaysdescribed with respect to FIG. 8: For example, if the device isoperating according to an embodiment as in FIG. 8 and the receivedcommand is one specifying a delay time, then, in step 805 or 813, thisvalue would override the value computed according to the algorithm.

Returning back to controller determined delay embodiment of FIG. 8, thisuses an assumption that the intervals between commands correspond to thenumber and type of applications that are executed on the host. Thistypically means there are periods where the commands will be veryfrequent and other times when the time between commands will be longer.The exemplary algorithms are simply implemented and are aimed atchanging the delay time before switching to the low-power standby mode,based on the last known command intervals. Here, it should be noted thatif a command is received after the card has already lapsed into thelow-power standby mode, the device will usually have no way to measurethe amount of time passed until the command was received since the sleepmode usually involves shutting down any sort of clock or oscillator thatcould be used for this. The suggested algorithms allow the controller tooptimize the memory system's power consumption in variable commandtiming environment.

CONCLUSION

For any of the described embodiments, these have the advantage ofproviding minimal low-power/regular mode switching overhead to gainmaximum input/output operation rate for any host and any hostapplication use case, whereas the previous approaches are based on astatic solution to provide a fixed response for all hosts andapplications

The foregoing detailed description of the invention has been presentedfor purposes of illustration and description. It is not intended to beexhaustive or to limit the invention to the precise form disclosed. Manymodifications and variations are possible in light of the aboveteaching. The described embodiments were chosen in order to best explainthe principles of the invention and its practical application, tothereby enable others skilled in the art to best utilize the inventionin various embodiments and with various modifications as are suited tothe particular use contemplated. It is intended that the scope of theinvention be defined by the claims appended hereto.

It is claimed:
 1. A method of operating a non-volatile memory system,the memory system including a non-volatile memory circuit and acontroller circuit for managing data stored in the non-volatile memorycircuit and the interactions between the memory system and a host towhich the memory system is connected, the method comprising: whileconnected to the host, operating of the memory system by the controllercircuit in one of either a standard mode or a low-power standby mode,including: operating the memory system in the standard mode whenexecuting host commands; after executing a host command, lapsing fromthe standard mode into the low-power standby mode after a delay unlessreceiving a further command from the host prior to lapsing into thestandby mode; and in response to receiving a host command while in thestandby mode, reverting to the standard mode; and while connected to thehost, operating the memory system according to a set of host commands,wherein the set of host commands includes one or more commands thatspecify a value for the delay subsequent to the execution thereof. 2.The method of claim 1, wherein the set of host commands further includesone or more commands that do not specify a delay value.
 3. The method ofclaim 2, wherein commands that do not specify a delay value use adefault value.
 4. The method of claim 1, wherein the memory systemmaintains a default value for the delay value in the non-volatilememory.
 5. The method of claim 4, wherein the controller circuitincludes a volatile random access memory transfers default value for thedelay value from the non-volatile memory to the volatile random accessmemory upon initialization.
 6. The method of claim 1, wherein thecontroller circuit includes a volatile random access memory maintainsthe delay value in volatile random access memory.
 7. The method of claim1, wherein commands that specify a value for the delay further specifywhether the specified value is to be subsequently used as a defaultdelay value.
 8. The method of claim 1, wherein commands that specify avalue for the delay further specify the type of commands to which thedelay value applies.
 9. The method of claim 1, wherein the memory systemmaintains a maximum value for the delay value in the non-volatilememory.
 10. The method of claim 1, wherein the low-power standby modediffers from the standard mode in that the low-power standby modeincludes turning off power to the memory circuit.
 11. The method ofclaim 1, wherein the low-power standby mode differs from the standardmode in that the low-power standby mode includes turning off a clockcircuit of the memory system.
 12. The method of claim 1, wherein thelow-power standby mode differs from the standard mode in that thelow-power standby mode includes turning off power to portions of thecontroller circuit.
 13. A non-volatile memory system, comprising: anon-volatile memory circuit; and a controller circuit connected tonon-volatile memory circuit, where the controller circuit manages thetransfer of data between the memory circuit and a host to which thememory system is connected and the storage of the data on the memorysystem, the controller circuit including logic circuitry and a volatilerandom access memory, wherein, in response to the memory system notreceiving a host command within in a period of time specified by a delayparameter, the controller places the memory system into a low-powerstandby mode, wherein the controller maintains a first value for thedelay parameter in the non-volatile memory circuit, and wherein thecontroller resets the value of the delay parameter in response to acommand that specifies a value for the delay parameter different thanthe first value.
 14. The non-volatile memory of claim 13, wherein thememory system transfers the first value for the delay parameter to thevolatile random access memory upon initialization.
 15. The non-volatilememory of claim 14, wherein the controller resets the value of the delayparameter in the volatile random access memory in response to saidcommand.
 16. The non-volatile memory of claim 15, wherein the controllerfurther resets the first value in response to said command.
 17. Thenon-volatile memory of claim 13, wherein, in response to the memorysystem said command while in the low-power standby mode, the controllerplaces the memory system into a standard operating mode and subsequentlyexecutes the command and resets the value of the delay parameter. 18.The non-volatile memory of claim 13, wherein the controller maintains amaximum value to which the delay parameter may be set in thenon-volatile memory circuit.
 19. The non-volatile memory of claim 13,wherein, in response a subsequent command, the controller further resetsthe value of the delay parameter.
 20. The non-volatile memory of claim13, wherein the low-power standby mode differs from a standard mode inwhich the memory system can execute host command in that the low-powerstandby mode includes turning off power to the memory circuit.
 21. Thenon-volatile memory of claim 13, wherein the low-power standby modediffers from a standard mode in which the memory system can execute hostcommand in that the low-power standby mode includes turning off a clockcircuit of the memory system.
 22. The non-volatile memory of claim 13,wherein the low-power standby mode differs from a standard mode in whichthe memory system can execute host command in that the low-power standbymode includes turning off power to portions of the controller circuit.23. A method of operating a non-volatile memory system, the memorysystem including a non-volatile memory circuit and a controller circuitfor managing data stored in the non-volatile memory circuit and theinteractions between the memory system and a host to which the memorysystem is connected, wherein the controller circuit operates the memorysystem in one of either a standard mode or a low-power standby mode, andwherein the memory system executes commands from the host in thestandard mode and lapses from the standard mode into the low-powerstandby mode after a delay value unless receiving a further command fromthe host prior to lapsing into the standby mode, the method comprising:monitoring by the controller of a plurality of commands from the host tothe memory system; based on said monitoring, determining the timebetween the commands; and optimizing by the controller of the delayvalue based on the time between the commands.
 24. The method of claim23, wherein the plurality of commands includes a first command and asecond command, the second command being the first subsequent commandreceived by memory system after the first command, wherein saidoptimizing includes: in response to receiving the second command whilein the standard mode, shortening the delay value.
 25. The method ofclaim 24, wherein shortening the delay includes setting the delay valueto be intermediate to the current delay value and the time between thefirst and second commands.
 26. The method of claim 23, wherein theplurality of commands includes a first command and a second command, thesecond command being the first subsequent command received by memorysystem after the first command, wherein said optimizing includes: inresponse to receiving the second command while in the standby mode,reverting to the standard mode; and once in the standard mode, executingthe second command and lengthening the delay value.
 27. The method ofclaim 26, wherein lengthening the delay includes setting the delay valueto be intermediate to the current delay value and a maximum delay value.28. The method of claim 27, wherein said maximum delay value is asettable parameter for the memory system.
 29. The method of claim 27,wherein lengthening the delay includes setting the delay value to beincreased by a fraction of the difference between the current delayvalue and the maximum delay value
 30. The method of claim 29, whereinthe fraction is a settable parameter for the memory system.
 31. Themethod of claim 29, wherein the fraction is dynamically determined bythe controller circuit.
 32. The method of claim 23, wherein operating inthe low-power standby mode includes turning off power to the memorycircuit.
 33. The method of claim 23, wherein operating in the low-powerstandby mode includes turning off a clock circuit of the memory system.34. The method of claim 23, wherein operating in the low-power standbymode includes turning off power to portions of the controller circuit.35. The method of claim 23, wherein the memory system maintains a copyof the delay value in non-volatile memory.
 35. The method of claim 35,wherein the memory system transfers a copy of the delay value from thenon-volatile memory to volatile memory on the controller circuit atinitialization.